Formally Embedding Existing High Level Synthesis Algorithms

This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations. Algorithms that ar

Formal Specification and Verification Techniques for RISC Pipeline Conflicts

this paper, the described formalization and proof strategies are illustrated via the DLX RISC processor. 1 Introductio

Implementing a Methodology for Formally Verifying RISC Processors in HOL

. In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels, so that the overall specification is correct with respect to its hardware implementation. The correctness proofs have been split into two steps so that the parallelism in the execution due to the pipelining of instructions, is accounted for. The first step shows that the instructions are correctly processed by the pipeline and the second step shows that the semantic of each instruction is correct. We have implemented the specification of the entire model and performed parts of the proofs in HOL. 1 Introduction Completely automating the verification of general complex systems is practically impossible. Hence appropriate heuristics for specific classes of circuits such as finite state machi..

An Automata Theory Dedicated towards Formal Circuit Synthesis

We present a theory for automata in HOL, which is dedicated towards formal hardware synthesis. The theory contains definitions for formally representing and transforming automata. In this approach hardware is represented by automata descriptions and formal synthesis is performed by applying formally proven theorems. The approach presented is constructive --- i.e. starting from specifications at higher levels of abstractions, synthesis can be performed by repeated applications of these transformations. Specialized refinements and optimizations at the RT and gate levels are discussed